(1) Field of the Invention
The present invention relates to a circuit for obtaining accurate timing information from a received signal.
In synchronous digital data receivers, the receiver clock must be continuously synchronized in frequency and phase with the received data signal to optimize the sampling timing of the received data signal and to compensate for frequency drift between the transmitter of the data signal and the receiver clock.
For that purpose, generally, timing information is extracted from a received data signal in synchronous digital data receivers.
(2) Description of the Related Art
FIG. 1 shows a part of a conventional construction for extracting timing information from a received data signal.
In FIG. 1, reference numeral 11 denotes a line equalizer, 12 denotes a level shift circuit, 13 denotes a tank circuit, 14 denotes a limiter circuit, 15 denotes a rectifier circuit, and 16 denotes a pulse generator.
The line equalizer 11 equalizes, i.e., compensates for a distortion of a wave shape of the received data signal that is induced by the characteristics of a transmission line through which the data signal has been transmitted from a transmitter.
The equalized data signal is level-shifted by the level shift circuit 12, and is then input into the tank circuit 13.
The tank circuit 13, which is a pass-band circuit consisting of an L-C resonance circuit, extracts a band of frequency components including a predetermined clock frequency of the communication system at the center, from the output of the level shift circuit 12.
The output of the tank circuit 13 is input into the limiter circuit 14, and is then transformed into a rectangular shape, i.e., to a digital bipolar signal. The digital bipolar signal is rectified in the rectifier 15, and is then input into the pulse generator, which is realized by a phase-lock loop (PLL) circuit 16, as a reference timing signal.
FIG. 2 shows the construction of a conventional digital phase-lock loop (DPLL) circuit, as an example of PLL circuit 16 used in the construction of FIG. 1.
In FIG. 2, reference numeral 20 denotes a master oscillator, 21 denotes a 1/2 frequency divider, 22 denotes a selector, 23 denotes a 1/N frequency divider, 24 denotes a phase comparator, and 25 denotes a jitter protection circuit.
A master oscillator 20 generates a master clock, and the master clock is frequency-divided in the 1/2 frequency-divider 21. The 1/2 frequency-divider 21 outputs two types of frequency-divided timing signals, a 0-phase signal and a .pi.-phase signal, where the phases of two signals differ in phase by .pi..
The selector 22 selects one of the 0-phase and .pi.-phase signals under the control of the output of the jitter protection circuit 25, as described in the following. The output of the selector 22 is then input into the 1/N frequency divider 23. The output of the 1/N frequency divider 23, which is the receiver clock (regenerated clock), is input into the phase comparator 24, and then is compared with the above output of the rectifier 15.
The comparison result in the phase comparator 24 is output in a form of an up/down signal to the jitter protection circuit 25.
The jitter protection circuit 25 is, for example, made by an up/down counter, and increments or decrements its count according to whether it is receiving an up signal or a down signal from the phase comparator 24.
In the up/down counter, a maximum and a minimum counts are preset, and the initial count is set to a value between the maximum and minimum counts. Therefore, until the difference between the number of the up signals input and the number of the down signals input, exceeds the difference between the maximum and the initial count, or the difference between the number of the down signals input and the number of the up signals input, exceeds the difference between the initial count and the minimum, i.e., unless a substantial frequency (phase) difference is detected in the PLL loop, no effective output is applied to the selector 22 as the control input.
The output of the selector 22 is switched from the 0-phase signal to the .pi.-phase signal when receiving an overflow output of the up/down counter 25, and therefore, the phase of the output of the selector 22, i.e., the phase of the output of the PLL circuit is delayed. The output of the selector 22 is switched from the .pi.-phase signal to the 0-phase signal when receiving an underflow output of the up/down counter 25, and therefore, the phase of the selector 22, i.e., the phase of the output of the PLL circuit is advanced.
However, recently, there has been a strong demand for realization of an LSI circuit to reduce the scale of the circuitry and power loss. Nevertheless, it is impossible to realize the tank circuit 13 which includes a L-C circuit, in an LSI.
To realize circuitry to extract timing information from a received data signal in an LSI, a method comprising a step of obtaining a sampled impulse response value from sampled levels of the received data signal and data symbols detected from the received data signal through a calculation using a digital filter, is proposed by Muller et al. in IEEE trans. COM. vol. COM. 24, NO. 5, May 1976, pp 516.about.pp 531.
Generally, in a synchronous baseband data transmission system with an overall impulse response h(t), the output of the system, e.g., the output of a line equalizer in a receiver, is expressed as ##EQU1## where a.sub.k is a data symbol, T is a period of the transmitter clock, and 0.ltoreq.k.ltoreq.L, wherein it is supposed that an impulse response does not extend beyond the time LT from the timing of a peak of the impulse response.
If the level of the received data signal x(t) is sampled at the period T, as x(t), x(t+T), x(t+2T), . . . x(t+LT), a series of sampled impulse responses h(t), h(t+T), h(t+2T), . . . h(t+LT) can be obtained as a solution of a linear equation system consisting of a set of linear equations ##EQU2##
In the prior art, it is noted that the following two types of functions f.sub.A (.tau..sub.A) and f.sub.B (.tau..sub.B) become zero if the output of the line equalizer is a superposition of a plurality of ideal Nyquist pulses, each of which becomes O at t=T, and -T: EQU f.sub.A (.tau..sub.A)=1/2[h(.tau..sub.A +T)-h(.tau..sub.A -T)](type A) EQU and EQU f.sub.B (.tau..sub.B)=h(.tau..sub.B +T) (type B)
where .tau..sub.A and .tau..sub.B are each a sampling phase.
FIG. 3 shows principles of the above-mentioned conventional methods for obtaining timing information from a received data signal.
In FIG. 3, h.sub.0 denotes h(.tau.), h.sub.-1 denotes h(.tau.-T), and h.sub.+1 denotes h(.tau.+T).
In the method shown as type A, the sampling phase .tau..sub.A is controlled so that the function f.sub.A (.tau..sub.A) is brought to zero, and in the method shown as type B, the sampling phase .tau..sub.B is controlled so that the function f.sub.B (.tau..sub.B) is brought to zero.
FIG. 4 shows the construction for carrying out the above-mentioned conventional type B method for obtaining timing information from a received signal.
In FIG. 4, reference numeral 30 denotes a sampling circuit, 31 denotes a data symbol discriminating circuit, 32 denotes an impulse response calculation circuit, and 33 denotes a comparator.
The sampling circuit 30 samples a level of a received data signal x(t) at a sampling phase, e.g., at the timing of the leading edge of the receiver clock, in each period.
The data symbol discriminating circuit 31 determines the data symbol of each time slot by discriminating the level of the received data signal x(t) at a phase, e.g., at the timing of the leading edge of the receiver clock, in each period.
FIG. 5 shows a timing of sampling a level x.sub.k of a received signal x(t), and discriminating a data symbol a.sub.k in a received signal.
FIG. 6 shows the construction of an example of an impulse response calculation circuit.
In FIG. 6, reference numerals 41 to 44 each denote a delay circuit with a delay time T, 45 to 47 each denote a multiplier, 48 denotes a weight calculation circuit, and 49 denotes a summation circuit. The period of the receiver clock is used for T, instead of the period of the real transmitter clock, which can be known indirectly in the receiver, i.e., as timing information extracted from the received data.
From the above-mentioned linear equation system, the impulse response h.sub.+1 =h(.tau.+T), and generally, h(t) is expressed in the following form. ##EQU3## where W.sub.n 's are each a weight, and a function of the data symbols a.sub.k.
Namely, the weight calculation circuit 48 calculates the above weights W.sub.n, W.sub.n-1, W.sub.n-2, . . . , the multipliers each carries out a multiplication W.sub.n .times.X.sub.n, W.sub.n-1 .times.X.sub.n-1, W.sub.n-2 .times.X.sub.n-2 . . . , and the summation circuit 49 carries out a summation of these terms. Thus, the impulse response h(t) is obtained from the construction of FIG. 6.
However, in the above method, the function f.sub.A (.tau..sub.A) or f.sub.B (.tau..sub.B) does not become zero even when the sampling phase .tau..sub.A or .tau..sub.B is at the optimum phase, i.e., at the peak of the impulse response, due to noise and a residual distortion after the equalization. For example, a line impedance between the transmitter and the receiver varies during the operation of the communication system because a line is temporarily formed arbitrarily between two subscribers in a public telephone network system. Further, in some types of equalization, e.g., .sqroot.f equalization, the equalized wave shape is not symmetrical regarding t=.tau., and a non-zero impulse response in a pre-cursor (t=.tau.-T) or in a post-cursor (t=.tau.+T) is essential, as shown later.
FIG. 7 shows an example of the situation in which an error in a phase of the receiver clock is induced due to a distortion of an overall wave shape of an impulse response.
Namely, the method for obtaining timing information from a received data signal in the prior art is greatly affected by residual distortion after equalization, noise, or a wave shape of equalization.
On the other hand, at an initial pull-in operation, generally, an initial sampling phase is random, i.e., the initial sampling phase may be far from the optimum phase for sampling.
In the prior art, by whatever method the timing information in the received signal may be obtained, the operation to shift the phase of the receiver clock toward the optimum phase is carried out gradually as an accumulation of small shifts, for example, in a digital PLL circuit in FIG. 2, as explained before.
Namely, in the prior art, it takes a long time for the phase of the receiver clock to converge to the optimum phase.